Document Type

Conference Proceeding

Publication Date


Publication Title

Proceedings of the Sixth MIT Conference on Advanced Research in VLSI



Publisher Name

MIT Press

Publisher Location

Cambridge, MA


This paper shows that a fat-pyramid of area Theta(A) built from processors of size lg A requires only O(lg^2 A) slowdown in bit-times to simulate any network of area A under very general conditions. Specifically, there is no restriction on processor size (amount of attached memory) or number of processors in the competing network, nor is the assumption of unit wire delay required. This paper also derives upper bounds on the slowdown required by a fat-pyramid to simulate a network of larger area in the case of unit wire delay.




This is the author's version of the work. It is posted here by permission of MIT Press for personal use, not redistribution. The final version of the work was published in William J. Dally (Ed.). 1990. Proceedings of the Sixth MIT Conference on Advanced Research in VLSI. MIT Press, Cambridge, MA, USA.

A revised version can be found at

Creative Commons License

Creative Commons License
This work is licensed under a Creative Commons Attribution-Noncommercial-No Derivative Works 3.0 License.

Greenberg1990_slides.pdf (8228 kB)
Presentation slides from Sixth MIT Conference on Advanced Research in VLSI, augmented by ending slides on extension to 3 dimensions (based on the paper that can be found at ).