Proceedings of the Sixth MIT Conference on Advanced Research in VLSI
This paper shows that a fat-pyramid of area Theta(A) built from processors of size lg A requires only O(lg^2 A) slowdown in bit-times to simulate any network of area A under very general conditions. Specifically, there is no restriction on processor size (amount of attached memory) or number of processors in the competing network, nor is the assumption of unit wire delay required. This paper also derives upper bounds on the slowdown required by a fat-pyramid to simulate a network of larger area in the case of unit wire delay.
Greenberg, Ronald I.. The Fat-Pyramid: A Robust Network for Parallel Computation. Proceedings of the Sixth MIT Conference on Advanced Research in VLSI, , : 195-213, 1990. Retrieved from Loyola eCommons, Computer Science: Faculty Publications and Other Works, http://dx.doi.org/10.1.1.55.6540
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MIT Press ©1990
Presentation slides from Sixth MIT Conference on Advanced Research in VLSI, augmented by ending slides on extension to 3 dimensions (based on the paper that can be found at http://ecommons.luc.edu/cs_facpubs/90 ).
This is the author's version of the work. It is posted here by permission of MIT Press for personal use, not redistribution. The final version of the work was published in William J. Dally (Ed.). 1990. Proceedings of the Sixth MIT Conference on Advanced Research in VLSI. MIT Press, Cambridge, MA, USA. http://dl.acm.org/citation.cfm?id=101415
A revised version can be found at http://ecommons.luc.edu/cs_facpubs/100.